1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to controlling a flash memory and more particularly to controlling flash memory that updates control information of a flash memory stored in a predetermined volatile memory when the type of flash memory is changed and controls the changed flash memory using the updated control information.
2. Description of the Related Art
A flash memory is a nonvolatile memory to which power is continuously supplied, and the contents of a flash memory can be erased and reprogrammed in terms of blocks. The flash memory is a modification of an Electrically Erasable Programmable Read-Only Memory (EEPROM). Unlike the EEPROM, in which the contents can be erased and corrected in terms of bytes, in the flash memory, since the contents are corrected in blocks, a processing speed to erase and correct contents is high. The flash memory is often used to store control codes, such as Basic Input/Output System (BIOS) of a Personal Computer (PC). When the BIOS needs to be corrected, the contents are recorded in blocks in the flash memory, not bytes, and thus the correction is easily performed. However, unlike the existing Random Access Memory's (RAMs), the flash memory is not useful since addresses are assigned in bytes, not blocks.
The flash memory obtains its name because a flash memory microchip is constructed such that portions of memory cells on the microchip can be erased by only one operation like a flash. Erasure is performed by a Fowler-Nordheim tunneling effect. That is, electrons pass through a thin dielectric material and eliminate charges from floating gates respectively connected to the memory cells.
The flash memory is an active device that receives commands from a programmer and executes the commands, not a passive device that merely has a storage device, a refresh circuit, and an error correction circuit, such as Dynamic RAM (DRAM). The commands are issued by a Command User Interface (CUI), and the entire status of the system is managed by a Write State Machine (WSM). The kind of the commands to be provided include a reading command, a writing command, and other control commands.
FIG. 1 is a diagram showing a known flash memory control system. The flash memory control system has a flash memory controller 10 and a flash memory 20.
Here, the flash memory controller 10 has a core processor 11, a One Time Programmable (OTP) memory 12, a status checking unit 13, and a control code transmitting unit 14.
The OTP memory 12 stores control codes for controlling the flash memory 20. The control codes include a reading control code, a writing control code, a reset control code, a block locking control code, and the like.
The status checking unit 13 checks the status of the flash memory 20. That is, the status checking unit 13 checks whether the flash memory 20 is in an active mode or in a standby mode.
The control code transmitting unit 14 transmits the control codes stored in the OTP memory 12 to the flash memory 20.
The core processor 11 refers to the status of the flash memory 20 checked by the status checking unit 13 so as to extract a control code from the OTP memory 12, and causes the control code transmitting unit 14 to transmit the extracted control code. Then, the core processor 11 performs the overall control of the OTP memory 12, the status checking unit 13, and the control code transmitting unit 14.
In the conventional flash memory control system described above, since only control codes for a specified flash memory are stored, when the kind of a flash memory is changed, the flash memory controller 10 cannot control a new flash memory.
Accordingly, in order to control flash memories having different control information, an additional flash memory controller including an OTP memory, in which corresponding control codes are stored, is required, which leads to an increase in costs.
In U.S. Patent Publication No. 2005-182893, there is disclosed a memory system that includes a memory controller controlling an access to a nonvolatile memory and a volatile memory in response to a memory request and having a memory storing address information of data stored in the volatile memory, a NAND flash memory, and a RAM storing data of the NAND flash memory.
In this case, however, in order to store data of the NAND flash memory in the RAM, an additional process needs to be executed, which causes inconvenience. For example, in order to sequentially control different flash memories, whenever the flash memory is replaced, a user needs to store data of a new NAND flash memory.
Accordingly, a technology that allows the control of different flash memories to be executed in a simple manner is needed.